1. Field of the Invention
This invention relates generally to non-volatile semiconductor memory devices, and more particularly to an electrically erasable and programmable semiconductor memory system that includes an array of memory cells, including series circuits of NAND type memory cells.
2. Description of the Related Art
With the increasing needs for high performance and high reliability of digital computer systems, it is demanded more and more to develop a large-capacity non-volatile semiconductor memory that can replace an existing external data-storage medium, such as a magnetic diskette, a fixed disk unit (which is sometimes called a "hard disk unit"), or the like.
Recently, to fulfill the expanding end-user's demands, a specific electrically erasable programmable non-volatile read-only memory (EEPROM) has been proposed and developed, wherein the integration density of memory cells is greatly enhanced by reducing the number of necessary transistors on a chip substrate of limited size. The EEPROM of this type is generally called a "NAND cell type EEPROM," in which a plurality of series arrays (circuits) of memory cell transistors are connected to bit lines by way of switching transistors, respectively. The memory cell transistors are floating gate metal oxide semiconductor field effect transistors (MOSFETs). When a switching transistor turns on, one cell transistor array is selectively connected to a corresponding bit line associated therewith. This switching transistor is called a "select transistor." The series arrays of cell transistors may be called the "NAND cell units."
Each NAND cell unit includes four, eight, or sixteen floating gate type MOSFETs as their minimum storage elements. Each MOSFET has a control gate connected to a corresponding word line, and a floating gate for storing charge carriers representing a logic "1" or "0" data. Since each "memory cell" includes only one transistor, the integration density of the EEPROM is improved to increase the total storage capacity thereof.
With the presently available NAND type EEPROMs, during a write operation, non-selected memory cells in each NAND cell unit function as transfer gates to transfer a data-bit to a target cell being presently selected. For convenience of explanation, the following discussion is made with respect to one NAND cell unit. A select transistor associated the NAND cell unit turns on causing this cell unit to be connected to a corresponding bit line. Those memory cell transistors between the select transistor and the selected cell transistor are externally controlled to turn on. A write data may have a particular logical value, "1" or "0." Assuming that the write data is a "1," the data voltage supplied from the bit line is transferred to the selected cell transistor via those turned-on transistors. Charge carriers are thus injected from the drain electrode into the floating gate of the selected cell transistor, thereby to charge it. The threshold value of the selected transistor changes, allowing the 1-bit data to be written or programmed therein.
To improve the operating reliability, a specific requirement is placed on the non-selected memory cell transistors acting as the transfer gates in the write operation: Their threshold values should be limited in the variation range. These transistors are prohibited from fluctuating beyond an allowable variation range; otherwise, the write voltage for the selected cell itself varies among NAND cell units, which will decrease the programming reliability. With well-known programming techniques used in the existing NAND type EEPROMs, it is not easy to meet the requirement. This is because most memory cell transistors on a one-chip substrate inherently exhibit different threshold values to be caused by variations in the manufacturing processes and the physical conditions. This fact may undesirably allow that relatively easy-to-write cells coexist with comparatively hard-to-write cells on the same chip substrate. Consequently, it is impossible to expect all addressing operations to be done in a uniformly organized manner. In addition, the operating reliability cannot be maintained at a desired level.